In order to improve the operating performance, there is in the prior art a one-chip microcomputer which has a multiply and accumulation unit mounted thereon for executing a specific operation with a smaller cycle number. On the so-called "RISC processor", as described on pp. 99 to 112 of Nikkei Electronics published on Nov. 23, 1992, there is mounted a multiply and accumulation module in addition to the general-purpose CPU so that the multiply and accumulation operations to be frequently executed in the digital signal processing may be executed in a smaller number of cycles.
For the higher performance, moreover, there is an example which is equipped with the multiply and accumulation unit capable of executing a plurality of identical operations simultaneously in parallel.
An example of Japanese Patent Laid-Open No. 83624/1994 is equipped with first and second execution lines which have a set of a data memory and an execution unit so that they can be simultaneously processed and independently processed, if necessary, with control signals coming from an instruction decoder.
In another publication of Japanese Patent Laid-Open No. 282926/1991, a floating point operation unit is provided as the data operation module so that the individual functions of the single-precision data operation/double-precision data operation/single-precision two-parallel data operation are realized with a common execution unit by switching modes.
In still another publication of Japanese Patent Laid-Open No. 94328/1991, the multiplier is exemplified by realizing the individual functions of the single-precision data operation/double-precision data operation/single-precision two-parallel data operation with a common hardware.
The techniques, as disclosed in the above-specified three Laid-Opens, are intended to improve the performance while suppressing the enlarged scale of the hardware by realizing the single-precision data operation and the single-precision two-parallel data operation by the common hardware.